The present invention is related to the fabrication process of semiconductor devices, particularly field effect transistors (FET""s) comprising L-shaped insulating spacers. These spacers are of particular interest for fabricating FET""s with a sub 0.25 xcexcm channel length.
Insulating spacers are widely used in the process of manufacturing integrated circuits. These spacers are mainly used for two important applications namely to isolate two conductive patterns one from another and as masking elements. Especially if their sole function is their use as masking elements, disposable spacers are often used. Disposable spacers are spacers which are removed later on in the process. However, for quite a number of applications permanent spacers are used because both their function as insulating elements as well as masking element is required. Examples of such permanent spacers can be found, e.g. in a FET, particularly in a FET with a lightly doped drain (LDD) and/or source, where the spacers are located at the sidewalls of the gate and are used to isolate the gate from the drain and/or source as well as to serve as a masking elements for the implantation of the highly doped drain/source regions. The formation of the (permanent) spacers is a very critical part of the manufacturing process because this spacer formation has a large influence on the definition of the intrinsic device and therefore on the device characteristics. Because the dimensions of the intrinsic device are very small, i.e. typically in the deep sub-micron range, one has to be able to define these spacers in a very controllable and reproducible way in order to be able to meet the stringent yield and reliability specifications. This problem will even be more stringent in the future due to the ongoing downscaling of the device dimensions.
In the past so-called lightly doped drain devices (LDD devices) have been introduced mainly to guarantee the specified operation during lifetime for a given supply voltage. This can be accomplished due to the electrical field lowering effect of lightly doped extensions. The major problems of such devices are:
establishing a well-defined and controllable overlap between the gate and the lightly doped source and drain extensions
establishing a well-defined and controllable offset between the lightly doped extensions and the respective (highly) doped source/drain regions in order to achieve a less steep doping gradient as compared with devices without extensions and thus a lower electrical field.
Conventionally the solution proposed to solve the overlap problem was either by means of out-diffusion of the as implanted lightly doped extensions (which were implanted self-aligned to the gate), or by means of LATID, where an implant under a large tilt angle is performed. To define an (extra) offset between the extensions and the respective source/drain regions, spacers adjacent to the gate of the device were used, i.e. lightly doped extensions were implanted self-aligned to the gate before the spacer formation, while the highly doped regions were implanted using the spacer as a mask. In the latter case contrary to the dimensions of the spacer, the precise shape of the spacer is not that important regarding the functionality of the device as long as the spacer isolates the gate from the drain/source regions and blocks the highly doped source/drain implantation. Remark that this conventional method requires two separate implantation steps and lithographic steps in order to form the source/drain regions, i.e. the highly doped regions as well as the extensions. Furthermore because the LDD implantation to form the extensions is in such an early stage of the process, the extensions are subjected to a large thermal budget.
Concerning sub 0.25 xcexcm CMOS and BiCMOS process generations, it is not likely that lightly doped extensions will still be required in field effect transistors in order to guarantee the specified operation during lifetime for a given supply voltage, due to the downscaling of the supply voltage. Hot carrier degradation is no longer a big issue, especially not for p-channel devices. However, the fabrication of shallow junctions, a low contact resistance to these junctions using silicide layers and a well defined and controllable gate overlap will be issues in these sub 0.25 xcexcm devices. Particularly because in se in conventional device concepts shallow junctions and a stable, reliable silicidation process are difficult to combine often resulting in a very limited process window.
The U.S. Pat. No. 5,702,986 is related to a process of forming L-shaped spacers and a process of forming LDD FET""s comprising such spacers. The L-shaped spacers are primarily introduced to limit mechanical stress. The spacer formation process of U.S. Pat. No. 5,702,986 is however a complicated process comprising dry and wet etching steps. Another disadvantage of this process is that the anisotropic spacer etch stops on/in the silicon substrate.
In an aspect of the invention, a scaleable device concept and a method for fabrication thereof is disclosed, which allows for a minimal well-controlled gate overlap by using low resistivity source/drain extension regions with shallow junctions. On the other hand, these new device concepts of the present invention facilitate the silicidation process because deeper source/drain contact regions can be used without influencing the gate overlap due to the fact that the gate overlap is defined by the extension regions and not by the source/drain contact regions. So, according to this aspect of the invention, a method for fabricating a field effect transistor on a substrate is disclosed, said substrate comprising at least one first part and at least one second part adjacent to said first part, said first part being covered with at least one first insulating layer and at least one conductive layer thereby forming a first area, i.e. e.g. the gate area of a FET, said second part being either uncovered or covered with said first insulating layer, thereby forming a second area, said method comprising the steps of:
a) forming a second insulating layer on said first and said second area, at least when said second part of said substrate is uncovered;
b) forming a third insulating layer on said second insulating layer or on said first and second area;
c) forming a disposable layer on said third insulating layer;
d) anisotropically etching said disposable layer using said third insulating layer as an etch stop layer to thereby form at least one spacer of said disposable layer on said second area adjacent to said first area;
e) removing said third insulating layer, using said spacer of said disposable layer as a mask;
f) removing said spacer of said disposable layer to thereby free the insulating spacer formed in said third insulating layer, said insulating spacer comprising a first portion being the base of said spacer, and a second portion, being the upright part of the insulating spacer adjacent to said first area; and
g) performing a source/drain dopant implantation using said first portion of said insulating spacer as a an element to lower the penetration depth of said implantation in said substrate thereby assuring that substantially the entire implantation dose penetrates at least into the part of the substrate below said first portion of said spacer. In other words, at least the extension regions are defined. Preferably, the insulating spacer formed is xe2x80x9cLxe2x80x9d-shaped.
In an embodiment of the invention, prior to the source/drain implantation, the first and the second insulating layer are removed using the insulating spacer formed in the third insulating layer as a mask.
In another embodiment of the invention a method is disclosed wherein said disposable layer is a silicon layer, e.g. a polysilicon or an amorphous silicon layer and wherein eventually, prior to the dry etching of said silicon layer, i.e. step d), first a native oxide, formed during exposure of said substrate to an ambient comprising oxygen, is removed. Alternative said disposable layer is a silicon (di)oxide layer.
In another embodiment of the invention, a method for fabricating a field effect transistor on a substrate is disclosed, wherein said substrate is placed in a chamber of an etch tool, said chamber having an ambient comprising HBr or a mixture of HBr and Cl2. Particularly in case step d) is performed, said ambient can further comprise a small amount of oxygen, i.e. typically less than 5%. Instead of a HBrxe2x80x94based chemistry also a fluorine based chemistry like e.g. CF4, or C2F6, or any other dry etch chemistry suited to remove the disposable layer selectively, i.e. typically with a ratio of about 3:1 or higher, from said third insulating layer can be applied. In case step e) is performed, said ambient can further comprise a small amount of oxygen, i.e. typically less than 5%. Instead of a HBrxe2x80x94based chemistry also any other dry etch chemistry suited to remove said third insulating layer selectively, i.e. typically with a ratio of about 2:1 or higher, to said spacer of a disposable layer can be applied. In case step f) is performed, i.e. the removal of the spacer of the disposable layer, said ambient can further comprise He or a mixture of He and oxygen, or instead of a HBrxe2x80x94based chemistry also any other dry etch chemistry suited to remove the remaining of said spacer of the disposable layer and eventually other residues selectively to said second and said third insulating layer. During steps d), e) and f) the substrate is located in a chamber of an etch tool, said chamber having a controllable ambient and being pressurized at a value substantially below the atmospheric pressure, i.e. typically in the range between 1 and 100 mTorr. Steps d), e) and f) can be performed without breaking vacuum, i.e. without exposing said substrate to the air and more particularly without switching the pressure between said value substantially below the atmospheric pressure and a value of about the atmospheric pressure. This can be done in a single chamber of an etch tool, or at least in a chamber of a single etch tool.
In another embodiment of the invention, said substrate comprising said first and said second region is placed in a chamber of an etch tool after said second and said third insulating layer and said disposable layer are formed on said first and said second region of said substrate. Thereafter, said substrate in said chamber can be subjected to a single removal process comprising dry etching steps d), e) and f) without breaking vacuum in said chamber. Particularly, for the formation of the spacer, preferably said spacer is a L-shaped spacer of an insulating material, a removal process is developed wherein in one removal sequence the remaining spacer of the disposable layer is removed as well as said L-shaped spacer of an insulating material is formed. By doing so, the introduction of an extra removal step, after breaking vacuum, to remove the spacer of the disposable layer is avoided. According to this embodiment of the invention, dependent on the precise etch chemistry, steps d) and e) or steps e) and f) or steps d), e) and f) can be combined by adapting and/or adjusting the flow of the chemicals and the pressure in the chamber. In the latter case, the single removal process comprises only one anisotropic dry etching step.
In another embodiment of the invention, a method is disclosed for forming a spacer on a substrate wherein said first, said second and said third insulating layer are selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides. Particularly, when said spacer is a nitride spacer and so and said third insulating layer is a nitride layer, preferably said second insulating layer is an oxide layer.
In another embodiment of the invention said at least one layer of said first region can be a polysilicon layer or an amorphous silicon layer or a combination of one of the previous layers and a silicide layer.
Further according to the method of the present invention, the distance, d2, being the sum of the width of the second insulating layer conformal to the side wall of the first region, i.e. the gate, and the width of the second portion of the insulating spacer, can be easily varied by varying the thickness of the second and/or the third insulating layer. Furthermore the width, d1, of the first portion of the insulating spacer can also be varied independently by changing the thickness of the disposable layer. Moreover, the thickness, t1, being at least the sum of the thickness of the first portion of the insulating spacer and the thickness of the insulating layers between said first portion and the underlying substrate, i.e. the second insulating layer or the first and the second insulating layer, can also easily be controlled by changing the thickness of the layer. In other words t1 is greater than or equal to d2. Therefore, dependent on the desired device performance, an insulating spacer with optimum dimensions can be formed to meet the performance specifications.
In another embodiment of the invention, the thickness, t1, is chosen such that the penetration depth of the source/drain implantation in the substrate is lowered by the insulating spacer and the underlying insulating layer. By doing so, not only highly doped source/drain contact regions are created adjacent to the spacer, but also ultra shallow highly doped extensions are created underneath the spacer because substantially the complete implantation dose penetrates into the substrate below the first portion of the insulating spacer, i.e. at least below the part of said first portion of the insulating spacer which is not covered by the second portion of the insulating spacer. As a result the gate overlap can be kept very small and well defined because the gate overlap can be fine tuned by optimising d2. Furthermore, on can also opt to perform an additional source/drain contact implantation after step d), i.e. after the formation of the disposable spacer, using the disposable spacer as a mask, potentially followed by a thermal treatment. By doing so, the source/drain regions are already formed and simultaneously in case a polysilicon or amorphous silicon gate is used, also the gate is doped.
In another aspect of the invention, a method for fabricating a field effect transistor on a substrate is disclosed, said substrate comprising at least one first part and at least one second part adjacent to said first part, said first part being covered with at least one first insulating layer and at least one conductive layer thereby forming a first area, said second part being either uncovered or covered with said first insulating layer, thereby forming a second area, said method comprising the steps of:
a) forming an oxide layer on said first and said second area, at least when said second part of said substrate is uncovered;
b) forming a nitride layer on said oxide layer or on said first and second area;
c) forming a disposable oxide layer on said nitride layer;
d) anisotropically etching said disposable oxide layer using said nitride layer as an etch stop layer to thereby form at least one spacer of said disposable oxide layer on said second area adjacent to said first area;
e) removing said nitride layer, using said spacer of said disposable layer as a mask to thereby define an insulating spacer in said nitride layer, said insulating spacer comprising a first portion being the base of said spacer, and a second portion, being the upright part of the insulating spacer adjacent to said first area;
f) removing said spacer of said disposable oxide layer and at least said oxide layer using said insulating spacer as a mask; and
g) performing a source/drain dopant implantation using said first portion of said insulating spacer as an element to lower the energy of said implantation thereby assuring that substantially the entire implantation dose penetrates at least into the part of the substrate below said first portion of said spacer. Particularly the step of removing said spacer of said disposable oxide layer and of said first and second oxide layer using said insulating spacer as a mask is executed using a HF-based wet etch solution. In case said first insulating layer is a silicon (di)oxide layer this layer can be removed by means of the same HF-based wet etch solution using said insulating spacer as a mask.